Tech-No!: Verification Methodologies and Design Patterns: A Preview

Ever since I worked on my first project in the industry, a simple Vera based verification environment, I have been thinking about the possible usage of Design Patterns in ASIC/SoC Verification. After all these years, I have managed to get a better understanding of this topic. I have worked on various Verification Methodologies and have identified a few design patterns in these methodologies.

In this series, I will target one design pattern in each post and hope to have a series of articles covering this topic. I will start with the usage of Singleton Pattern in OVM.