Tech-No!: Verification Methodologies and Design Patterns: A Preview

Ever since I worked on my first project in the industry, a simple Vera based verification environment, I have been thinking about the possible usage of Design Patterns in ASIC/SoC Verification. After all these years, I have managed to get a better understanding of this topic. I have worked on various Verification Methodologies and have identified a few design patterns in these methodologies.

In this series, I will target one design pattern in each post and hope to have a series of articles covering this topic. I will start with the usage of Singleton Pattern in OVM.

Tech-No!: The Ideal World of Verification

Ever wondered how an ideal world of verification would look like? I would probably see one when the following criteria are met.

• Infinite Budget
• No Deadlines or time limit
• Infinite resources, consisting of verification experts
• An amazing specification which captures every possible detail of the design and frozen
• A client or architect not making any change requests
• An amazing EDA tool which supports every possible feature
• A very high end machine grid to run your jobs

So what else would one need in this ideal world? Given that these are met how would your verification environment look like?